IEEE

Efficient Hardware Accelerator Design for AES Encryption Using High-Level Synthesis Techniques

Abstract: In this work, we present the design and implementation of a hardware accelerator for AES encryption and decryption using AMD Vitis HLS and Xilinx Vivado. The primary objective of this work ...
IEEE

Security of Sensitive Data in Face Recognition System Applications: A Novel Encryption Approach

Abstract: Background and Aim: The design of secure systems that can protect sensitive data is becoming a major area of research due to the growing number of applications that use the Internet. In ...