电子工程专辑

从VerilogPLI到SystemVerilogDPI的演变

写过Verilog和systemverilog的人肯定都用过系统自定义的函数$display，这是预定好的，可以直接调用的功能。但是当Verilog中的task和 ...
Design-Reuse

A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of ...

Complex system design requires modeling, testing, debug and analysis of many levels of abstraction with varying levels of accuracy. Reuse from previous steps is important at each step of the design ...
腾讯网

谈谈Verilog和SystemVerilog简史，FPGA设计是否需要学习SystemVerilog

SystemVerilog标准（SV-2009）发布距今已近十余年，在验证领域已经大放异彩，但是在设计领域（尤其FPGA领域）使用的还是比较少，虽然市场上已经发布了几本相关书籍，但是在使用上或者学习上还是有点缺陷的，这篇文章是SystemVerilog建模及仿真系列教程的第一篇 ...
电子工程专辑

谈谈Verilog/SystemVerilog和C的几种交互方式

最近有群友问我system Verilog 和C怎么交互，在网上搜了一圈发现资料比较少，今天这里就和大家讲讲system Verilog 和C的交互。话不多说直接上干货。 第一种 Verilog 通过PLI调用C函数。 PLI全称 Program Language Interface，程序员可以通过PLI在verilog中调用C函数，这种访问是 ...
Design-Reuse

Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI)

Riviera-PRO 2008.02 supports many features of the VHDL standard draft (IEEE P1076-2007/D4.0), recently approved by Accellera. Constructs such as new data types, subprograms and operators, matching ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...